1. Field of the Invention
The present invention relates to standard cell design and, in particular, to standard cells that can include phase information.
2. Discussion of the Related Art
Lithography is a well-known process used in the semiconductor industry to form lines, contacts, and other known structures in integrated circuits (ICs). In conventional lithography, a mask (wherein the term “mask” as used herein can refer to a mask or a reticle) having a pattern of transparent and opaque regions representing such structures in one IC layer is illuminated. The emanating light from the mask is then focused onto a photoresist layer provided on a wafer. During a subsequent development process, portions of the photoresist layer are removed, wherein the portions are defined by the pattern. In this manner, the pattern of the mask is transferred to (i.e. printed on) the photoresist layer.
However, diffraction effects at the transition of the transparent regions to the opaque regions on the mask can render the corresponding printed edges on the wafer indistinct, thereby adversely affecting the resolution of the lithography process. Various techniques have been proposed to improve the resolution. One such technique, phase shifting, uses phase destructive interference of the waves of incident light. Specifically, phase shifting shifts the phase of a first region of incident light waves approximately 180 degrees relative to a second, adjacent region of incident light waves to create a sub-wavelength feature between the first and second regions. Thus, a feature, as defined by exposed and unexposed portions of a photoresist illuminated through a mask, can be more closely defined by using phase shifting, thereby allowing greater structure density on the IC.
As the need for feature density increases, phase shifting is being applied to more features on the layout. In one embodiment, called a full phase approach, substantially all features of a layer can be defined using phase shifting. To maximize their effect, the phase shifting regions, hereinafter called shifters, can be made as large as possible in light of limitations presented by the input layout.
Typically, basic structures are used hundreds or even thousands of times on the same IC. Therefore, designers commonly use a standard cell library, wherein each cell includes one or more unique structures of varying complexity. Exemplary structures can include, for example, gates, latches, and flip-flops. These cells can then be used to build structures of greater complexity, such as memory, adders, and multipliers.
Because the physical layout for each cell is developed, using a standard cell library can result in a significantly reduced design turnaround time compared to “re-designing” a structure for each version in the layout. However, to take advantage of phase shifting in a typical standard cell methodology, shifters are inserted into the layout after place-and-route or even after design sign-off. Unfortunately, the time spent between sign-off and fabricating an IC can be the most critical part of a design schedule. Therefore, the time spent inserting shifters at this late stage can result in highly undesirable delays.
Moreover, inserting shifters in standard cell layouts can result in phase conflicts. Phase conflicts can negate the optical interference necessary to create the desired feature(s). Therefore, assigning phase to and resolving phase conflicts in the layout can constitute a time-intensive, but mandatory part of typical process flows in the production of many integrated circuits.
For these reasons, a need arises for a system and method of incorporating phase information into a standard cell methodology. This incorporation should provide a more time-efficient process as well as minimize phase conflict.